What is the VHDL timing constant?

I'm a beginner at VHDL.
I am studying by looking at the example description below.
http://kivantium.hateblo.jp/entry/2016/02/25/232858

in receiving state=1 elsif counter=1500then

to read the received data in the middle of the bit. 32 MHz / (9600x2) = 1666
I think it should be
but why it was made 1500
Please let me know.