About load linked/store conditional

MIPS instructions
There is an instruction called load linked/store conditional (LL/SC) and I don't know how they work.

<My Understanding>
Indivisible SWAP by LL and SC

LL Operation
①Specify an address in memory and determine if the value in the address is 1
②If the value is 1, do nothing because it is locked.If the value is 0, store the value of the address to be locked in the register

SC
①If you specify an address on memory and it is locked by a pair of LL instructions,
A register value is stored in an address on a memory.
②If が succeeds, set the value of the register to 1.If it fails, set it to zero.

<Question>
LL and SC itself seem to be complicated instructions including beq, but
Are these single instructions?

When LL and SC are a pair of instructions, they are written in "Computer Configuration and Design (above)" but do not understand the meaning of a pair of instructions.Do you say it's a pair because you use it continuously?

Do you mean that multiprocessors do not know which processor's instructions are executed in what order, so conflicts can occur, and if a processor's LL locks it, SC of the same processor can unlock it?