I have a question about the following article:
Computer Architecture Story (139) Direct Map Cache and Its Notes|TECH+ (Tech Plus)
The sixth paragraph from the end of the page above contains the following:
Originally, 8 bytes of read and 8 bytes of write were required, but 64 bytes of cache line read twice and write once, resulting in 24 times the amount of data transfer to memory.
I have a question about this, but I thought for a moment that the amount of data transfer would be 12 times as high as 8 bytes + 8 bytes = 16 bytes, and 64 bytes * (2 times + 1 time) = 16 * 12 bytes.The website says 24x, but why is it 24x instead of 12x?If anyone knows why, please let me know.
hardware cpu
the source of the question
Computer Architecture Story (139) Direct Map Cache and Its Notes|TECH+ (Tech Plus)
describes the following:
Then, if you try to load a[2] by adding i to +1, the cache line contains b, so this is also a mistake.
In this way, cache errors occur every time a and b access.Thus, the cache magic of reducing the number of access times to the main memory does not work well, and the data transfer volume of the 64-byte cache line is 24 times higher than that of the absence of cache.
Because of cache errors, when you read 64 bytes of data from memory into the cache, you must write back 64 bytes of cache to memory.
Therefore, memory transfers can be interpreted as twice as many as 64 bytes* (2 + 1) and 24 times more than 12 times.
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