I have a question about the following article:
Computer Architecture Story (139) Direct Map Cache and Its Notes|TECH+ (Tech Plus)
When I rewrite the data in the cache, do I rewrite all the data in the cache line at the same time?The above site reads and writes all b[0]~b[7] because cache errors occur after reading a[0]~a[7], but only one b[0] (at the same time, one of the a[0]~a[7] already on the cache line disappears from .
If anyone knows why, please let me know.
The address data to be stored in pairs with the data is called a tag (Tag, meaning a tag attached to a suitcase for overseas travel).The data-tag pair is then called the cache line.
As you can see on the site, the cache line has the same high-order address
Must be a continuous area accessible only by lower address
The reason, or rather, is the definition of the cache line
Simply read one b[0] (at the same time, overwrite one of the a[0] to a[7] already in the cache line
)If you're trying to do this, you don't know which one to take, the cache tag is a or b, so the number 0 is &a and 1-7 is &b.
Then you can set the cache line size to 1 and have different addresses in all the caches
I think, but if you do something so flexible in the hardware world, the circuit efficiency will be significantly worse
For example, cache lines are often 16 to 256, but
If the cache line is set to 1 compared to 16
16x address matching circuit is required.
You only need to have one higher address for 16 data.
You must have one parent address per data, and
Half the storage space available for data
I think it will probably appear in the future explanation
Intel's i7 or something is called 4-way set associative
You can have up to four cache lines with common lower addresses
In addition, for AMD, it's called Victim Cache.
Little cache lines that have been cached incorrectly
We mitigate cache errors by keeping them full-associated
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