Differences Between Asynchronous and Synchronous SRAMs

• Asynchronous SRAM

  1. The master addresses the address bus with the master clock
  2. The master enables ChipSelect (CE) on the master clock
  3. SRAM detects chip select changes in SRAM clock SRAM reads addresses in SRAM clock
  4. SRAM retrieves address data from the SRAM clock
  5. The SRAM clock in SRAM outputs to the data bus
  6. SRAM changes the output enable signal (OE) on the SRAM clock
  7. The master detects changes in the output effective signal on the master clock
  8. The master reads data from the data bus with the master clock
  9. The master disables chip select on the master clock
     　

• Synchronous SRAM

  1. The master addresses the address bus with a common clock (bus clock)
  2. SRAM reads addresses at the edge of the common clock
  3. SRAM extracts data from addresses with a common clock (it does not have to be a common clock for internal SRAM operations)
  4. SRAM common clock outputs clock to data bus (synchronized with bus clock)
  5. The master reads data from the data bus after a fixed clock with a common clock.

Asynchronous SRAM

Synchronous SRAM

Asynchronous needs to be communicated on different clocks, so we need to meet at the same time as CE and OE.
Instead, SRAM can operate on a free clock.
Use asynchronous if there is a deviation or deviation between the operating clock on the master side and SRAM.

As there are no meetings like CE and OE, there are few steps to synchronize, so we can communicate at high speed.
However, it is necessary to allow room for operation so that the clock does not lag behind, and it will operate below the SRAM operating limit.
The clock deviation between the master side and the SRAM is not allowed.(FPGA usually derives from a common clock, so it usually does not deviate.)

• burst
  Once addressed, it outputs data for consecutive addresses.

• Nonburst
  Once addressed, print only data for the specified address.

Burst
Once you address, you can output data for consecutive addresses.

US>Non-burst
Once addressed, print only the data for the specified address.

If you read data for consecutive addresses, you can reduce the addressing process by reading it in bursts and addressing it only once.Also known as sequential addresses, data extraction can be pipelined to accelerate.

You can create either a synchronous burst or an asynchronous burst because it's just a difference in addressing.
However, asynchronous bursts require OE changes for each data output, so there are more steps than synchronous bursts.Therefore, bursts are usually referred to as synchronous bursts.

Asynchronous Asynchronous Burst SRAM has more steps and more addressing times, so it is slow.
Synchronous burst SRAM itself is asynchronous in processing speed, but results in faster processing due to fewer steps and minimal addressing.

Asynchronous block-by-block speeds each block up to its limit with a free clock.However, if there is interaction between blocks, some kind of meeting will occur, so it is not always faster.

I'm not very confident, but...

It's the difference between asynchronous and burst mode.
Memory with burst mode simplifies access procedures.

If you want to access any memory address, ask the memory for the value of this address.This request happens every time, but burst mode is a way to ask for a value from here to here.
The next memory address you want to access is also generated in memory, so I think it will be faster as the steps are reduced.

http://h50146.www5.hp.com/products/servers/proliant/whitepaper/wp034_050501/p01.html