Why does the 8086 segment register have a width of 16 bits?

The answer to "why" is 16bit CPU as @y_waiwai said.If you go out of your way to prepare a 4-bit register, you will be troubled by PUSH/POP.

Another reason is that having multiple physical address conventions is more useful for implementing software.

If you want to copy data in the physical address [0x1EEE8,0x2345F] range from physical address 0x4FF08

• If the segment register is 4 bits
  A value of the segment register needs to be changed at a different timing, once at a copy source and once at a copy destination.Updating the segment register will recalculate the offset.

• If the segment register is 16 bits
  If the copy destination [0x1EEE:0x0008-0x1EEE:0x457F] is normalized to [0x4FF0:0x0008-], the segment register is not updated in the middle.Offset only

If the segment register is 4 bits
A value of the segment register needs to be changed at a different timing, once at a copy source and once at a copy destination.Updating the segment register will recalculate the offset.

If the segment register is 16 bits
If the copy destination [0x1EEE:0x0008-0x1EEE:0x457F] is normalized to [0x4FF0:0x0008-], the segment register is not updated in the middle.Offset only

It is easy for the software implementers to normalize at the start of a process without having to update the segment register while processing one object (=fast).Conversely, on 8086, if one object exceeds 64KiB in memory, the segment register must be updated during processing and is extremely slow.

The Renesas RL series seems to be a microcomputer with a 4-bit segment register. CS/ES is named as the register name to capture 8086 users, but the implementation is completely different.It's a design idea that small-scale microcomputers rarely handle more than 64KiB of data.

8086 is a 16-bit CPU, so all registers are 16-bit. In , the segment register requires 16 bits, so it is the width.
If you just want to express 1M, then 4 bits is enough, but that's not all.

If you have looked at the Wikipedia documentation, you should also carefully read the text immediately after the quoted text.
Simply put, it's because your question and the designer's emphasis are different.
I (quote) wrote in bold below, but I think that's important.

The following description continues on the Japanese page:

In the architecture of 8086, the value of the address normally expressed in the program is a memory space of 64 KB with a 16-bit width.At that time, 64KB of memory space was large enough for a single program [3], and segment mechanisms were prepared for multitasking.(The 8086 does not have protection, so the application can operate the segment register, but it is originally operated by the OS.) If all four built-in segment registers are the same, it is easy to port the source for the 8080 to 8086.

The segmentation method, which later became the focus of criticism, was a fast, compatible, cost-effective option.This was a critical factor for Intel, who was engaged in a fierce share battle with Motorola at the time.
It is also said that 1MB of memory space was a value that can be allocated efficiently by increasing the address pin when assigning the address data bus to the 40DIP package used at that time.

Furthermore, the English version of the page can be easily translated by Google, so if you look at it, you will find more details.Here are some of the statements that might apply:

Intel 8086-Wikipedia

Although it is considered complex and difficult to handle by many programmers, the scheme also has advantages.You can load small programs (less than 64 KB) from fixed offsets of your own segments (such as 0000) to avoid the need for relocation and save up to 15 bytes of alignment waste.

Morse et al. said [9] designers considered actually using an 8-bit shift (rather than 4 bits) to create 16 MB of physical address space, although this rejected the idea because the segment started at a 256-byte boundary and 1 MB was considered very large for microprocessors around 1976.Also, for the additional four address bus pins, there were not enough pins available in the low-cost 40-pin package.

Simply put, this is a trade-off.If memory addressing is simplified so that memory is accessed only in 16-bit increments, memory utilization is reduced.Intel has decided to make the logic more complicated, but memory usage is more efficient.This was a time when memory sizes were significantly smaller and more valuable than those users are using today. [10]:5–26

Porting old software
Small programs can ignore segmentation and use simple 16-bit addressing.This makes it very easy to port 8-bit software to 8086.In addition to providing a very similar application programming interface to CP/M, most DOS implementations were important when 8086 and MS-DOS were new.This is because it makes many existing CP/M (and other) applications available quickly and greatly facilitates the acceptance of new platforms.

There is also a page below, but it is close to repeating the above, so I will introduce only the link.
x86 memory segmentation-Wikipedia

By the way, there is the following description in the Japanese Wikipedia footnote.I think it took quite a while for us to be able to prepare a standard range of 1MB (actually 640KB) at a low price.

For your information, the first IBM PC had 64KB of RAM (16KB model but not sold) and the first NEC PC-9801 had 128KB of RAM.

For more information, you may find an IEEE article in a word document at the bottom of the English Wikipedia.
I can't say anything about it because I haven't read it yet.
Intel Microprocessors: 8008 to 8086 by Stephen P. Morse et al.
addition:
"When I read the article above, it seems that the ""why the segment register was 16bit"" itself is not written, but as @y_waiwai and @774RR wrote, it seems that the non-16bit register was not on the basis of consideration."
And segment boundaries were not adopted even at 256 bytes because of concerns about memory fragmentation.Not to mention 64KB boundaries.
Here are excerpts of possible references to:Bold letters are also from the citation.

VII.Objectives and Constraints of 8086

The goals of the 8086 architectural design were to provide symmetric extensions of existing 8080 features, and to add processing capabilities not found in the 8080.
These features included 16-bit arithmetical, signed 8-and 16-bit arithmetical (included multiply and divide), efficient interrupt byte-string operations, improved bit-management facilities, and mechanisms to provide for re-entrant code, position-current state. By now memory had been very exponential and microprocessors were being used in applications that required large amounts of code and/or data.
Thus another design goal was to be able to address directly more than 64k bytes and support multiprocessor configurations.

The goal of the 8086 architecture design was to provide symmetrical enhancements to existing 8080 features and to add processing features that the 8080 does not have.
These features include 16-bit operations, signed 8- and 16-bit arithmetic (including multiplication and division), efficient interruptible byte string manipulation, improved bit manipulation, mechanisms that provide re-entryable code, location-independent code, and dynamically relocatable programs.
Memory is now very inexpensive, and microprocessors were used in code and data-intensive applications.
Therefore, another design goal was to address 64 kbytes or more directly to support multiprocessor configurations.

VIII.The 8086 Instruction-Set Processor
A. Memory Structure 1.Memory Space.

Since the 8086 processor performances 16-bit arithmetic, the address objects it manipulates are 16 bits in length.
Since a 16-bit quality can address only 64K bytes, additional mechanisms are required to build addresses in a megabyte memory space.
The 8086 memory may be received of as an arbitrary number of segments, each at most 64K bytes in size.
Each segment begins at an address which is eventually divisible by 16 (i.e., the low-order 4 bits of a segment's address are zero).
At any given moment the contents of four of these segments are immediate addressable.
These four segments, called the current code segment, the current data segment, the current stack segment, and the current extra segment, need not be unique and may overlap.
The high-order 16 bits of the address of each current segment are held in a dedicated 16-bit segment register.
In the generate case where all four segments start at the same address, name address 0, we have an 8080 memory structure.

The 8086 processor performs 16-bit operations, so the address object it operates on is 16 bits long.
An additional mechanism is needed to build an address in megabytes of memory space, since the 16-bit amount can only address 64K bytes.
8086 memory can be any number of segments, each of which can be up to 64K bytes in size.
Each segment begins with an address divisible by 16 (that is, the lower four bits of the segment's address are zero).
At any time, the four contents of these segments can be addressed immediately.
These four segments are called the current code segment, the current data segment, the current stack segment, and the current additional segment, and do not have to be unique or can overlap.
The top 16 bits of the address of each current segment are kept in a dedicated 16-bit segment register.
If all four segments start with the same address, or address 0, then 8080 memory structures are present.

Various alternatives for extending the 8080 address space were considered.
One such alternative considered of appending 8rather than 4 low-order zero bits to the contents of a segment register, thereby provisioning a 24-bit physical address capable of addressing up to 16 megababytes of memory.
This was rejected for the following reasons:

• Segments would have been forced to start on 256-byte boundaries, resulting in exclusive memory fragmentation.
• The 4 additional pins that would have been required on the chip where not available.
• It was felt that a1-megabyte address space was sufficient.

Various options for expanding 8080 address space were considered.
One such alternative is to add 8 bits instead of the lower 4 bits to the contents of the segment register, providing a 24-bit physical address that can address up to 16 megabytes of memory.
This was rejected for the following reasons:

• The segment is forced to start at a 256-byte boundary, resulting in excessive fragmentation of memory.
• The four additional pins he needed on the chip were not available
• 1 megabyte of address space seemed sufficient

B.Register Structure
The 8086 processor contains three files of four 16-bit registers and a file of Nine 1-bit flags.
The three files of registers are the general-register file, the pointer-and index-register file, and the segment-register file.

The 8086 processor contains three files from four 16-bit registers and nine 1-bit flagged files.
The three files in the register are generic register files, pointer and index register files, and segment register files.

3. Segment-Register File.
Programs which do not load or manage the segment registers are said to be dynamically relocatable.
Such a program may be interrupted, moved in memory to a new location, and restarted with new segment-register values.

Programs that do not load or manipulate segment registers are referred to as dynamically relocatable.
Such programs are interrupted, moved to a new location in memory, and restarted with the new segment register value.

By the way, there is another manufacturer's CPU that adopted the same idea of address extension as you, but it was still a 16-bit register, and the unused bits were fixed to zero.
In fact, the combination of CPU and MMU (Memory Management Unit) chips ended up free to deploy on real memory, regardless of 64KB boundaries.

Z8000-Wikipedia

Basically, it's a 16-bit architecture, but with the exception of Z8002 for embedded systems, Z8001 uses a 7-bit segment register to expand its address, convert it to a real address in Z8010 (MMU), and expand its address space to 8M bytes.

Zilog Z8000 CPU Technical Manual.
Zilog Z8000 CPU User's Reference Manual.
Both have illustrations of the numbers below.
Figure 2-6.CPU Special Registers
Figure 3-3.Segmented and Non-Segmented Address Formats
Figure 3-4.Segmented Address Translation

By the way, 65816 is famous for its Super Fami-Con, but it seems that it uses an 8-bit segment register, which is not very easy to access on the web today.
I think there are a lot of people who are familiar with it, but there are few easy-to-understand materials such as illustrations on the web.

It's a strange CPU with 256 8-bit 6502s, or linear addressing like 68000 relatives.

65816 (Computer)
WDC65C816-Wikipedia
65816 Architecture SNES Laboratory
Modified Donkey House-SNES Technical Documents-65C816 Programming Reference-Register
Modified Donkey House-SNES Technical Documents-65C816 Programming Reference-Addressing Mode